Logic design by godse pdf
Memory refresh is the process of periodically reading information from an area of computer memory and immediately logic design by godse pdf the read information to the same area without modification, for the purpose of preserving the information. In a DRAM chip, each bit of memory data is stored as the presence or absence of an electric charge on a small capacitor on the chip.
SRAM circuits require more area, because an SRAM memory cell requires four to six transistors, compared to a single transistor and a capacitor for DRAM. While the memory is operating, each memory cell must be refreshed repetitively, within the maximum interval between refreshes specified by the manufacturer, which is usually in the millisecond region. The storage cells on a memory chip are laid out in a rectangular array of rows and columns. The read process in DRAM is destructive and removes the charge on the memory cells in an entire row, so there is a row of specialized latches on the chip called sense amplifiers, one for each column of memory cells, to temporarily hold the data. For a refresh, only the row address is needed, so a column address doesn’t have to be applied to the chip address circuits. Data read from the cells does not need to be fed into the output buffers or the data bus to send to the CPU.
The refresh circuitry must perform a refresh cycle on each of the rows on the chip within the refresh time interval, to make sure that each cell gets refreshed. Usually the refresh circuitry consists of a refresh counter which contains the address of the row to be refreshed which is applied to the chip’s row address lines, and a timer that increments the counter to step through the rows. This counter may be part of the memory controller circuitry, or on the memory chip itself. Distributed refresh – refresh cycles are performed at regular intervals, interspersed with memory accesses. Burst refresh results in long periods when the memory is unavailable, so distributed refresh has been used in most modern systems, particularly in real time systems. 64 ms and 8,192 rows, so the refresh cycle interval is 7. Recent generations of DRAM chips contain an integral refresh counter, and the memory control circuitry can either use this counter or provide a row address from an external counter.
RAS only refresh” – In this mode the address of the row to refresh is provided by the address bus lines, so it is used with external counters in the memory controller. In this mode the on-chip counter keeps track of the row to be refreshed and the external circuit merely initiates the refresh cycles. This mode uses less power because the memory address bus buffers don’t have to be powered up. It is used in most modern computers.
Hidden refresh” – This is an alternate version of the CBR refresh cycle which can be combined with a preceding read or write cycle. The refresh is done in parallel during the data transfer, saving time. RAS only” mode has been eliminated, and the internal counter is used to generate refresh. The chip has an additional “sleep mode”, for use when the computer is in hibernation, in which an on-chip oscillator generates internal refresh cycles so that the external clock can be shut down. 8,192 rows, a refresh interval of 64 ms, the memory bus runs at 133 MHz, and the refresh cycle takes 4 clock cycles.